The manufacture of integrated circuits on semiconductor wafers has continued to allow electrical devices to become more compact, yet with improved performance and greater capabilities. As a result, manufacturers are constantly improving on the manufacturing techniques and processes for the semiconductor devices forming these integrated circuits. In particular, silicon-on-insulator (SOI) technology is becoming an increasingly important field in the manufacture of integrated circuits. SOI technology deals with forming semiconductor devices, such as transistors, in a layer of semiconductor material overlying an insulating layer. The insulating layer is formed on an underlying substrate of a semiconductor wafer and electrically isolates the devices from other areas and devices of the integrated circuit. Electrical interconnects are then formed throughout the various layers of the wafer to interconnect the different devices to form the circuit.
Typically, such transistors include graded junction regions implanted into the semiconductor material on either side of a gate structure, and usually include HALO pockets, deep source/drain regions, graded source/drain regions, and lightly-doped drain (LDD) regions. The gate structure is formed on the surface of the semiconductor material, over a channel generally defined between the graded junction regions, which are typically formed deep into the semiconductor material and reach the insulating layer. To manufacture such devices, conventional processes form spacers adjacent the gate structure, and then perform an implant to form heavy-doped graded source/drain regions alongside the channel, yet still relatively far away from it. The spacers are then removed and more spacers arc formed, yet smaller in width, to dope the deep source/drain regions closer to the channel. LDDs, closest to the channel, are then formed resulting in graded junctions on either side of the channel. Throughout this process, light doping is usually used to specifically engineer the junction capacitance (Cj) of the graded junctions in an attempt to optimize device performance. While such problems may be avoided in SOI devices by simply omitting the graded implantation (since the Cj of SOI devices is small when compared to bulk device due to the insulating layer in SOI devices), the problems are exacerbated in bulk devices where the graded source/drain implants are needed to reduce the Cj and improve device performance.
Unfortunately, among the many problems that result from such conventional manufacturing processes, employing smaller spacers during the process usually requires a corresponding change in doping profile (e.g., lowering the dopant energy at each implant), often resulting in a penalty in the final Cj of the device. In addition, the material used to form the smaller spacers, typically nitride, often detrimentally affects the formation of acutely graded junctions in the device tubs, which is critical to optimizing device performance. Specifically, attempting to implant dopant through a nitride layer often detrimentally affects the accuracy in forming the graded junctions typically desired. Still further, the high temperature to which the wafer is typically subjected during the formation of spacers often causes unwanted diffusion of dopants implanted into the substrate. Accordingly, what is needed in the art is a method for manufacturing semiconducter devices that does not suffer from the deficiencies of conventional techniques, and that can be employed with both bulk devices and ultra-thin manufacturing techniques, such as ultra-thin SOI manufacturing.